Delay Analysis for Current Mode Threshold Logic Gate Designs

Abstract

Current mode is a popular CMOS-based implementation of threshold logic functions, where the gate delay depends on the sensor size. This paper presents a new implementation of current mode threshold functions for improved gate delay and switching energy. An analytical method is also proposed to identify optimum sensor sizes that minimize the gate delay. This allows us to design large threshold functions with delay much less than a network of CMOS gates. Simulation results on different gates implemented using the optimum sensor size indicates that the proposed current mode implementation method outperforms consistently the existing implementations in delay as well as switching energy.