Serial-Out Bit-Stage Mastrovito Multiplers for High Speed Hybrid Double Multiplication Architecture

Abstract

Serial-bit level multiplication scheme has important internal feature. As a result of the multiplication of each clock cycle to generate a bit of it one has the ability to output. However, $ GF $ ($ 2 ^ m $) is based on the representation of the general use of the multipliers in the existing serial bit-level computational complexity, which limits its usefulness for many applications; Thus, the optimum use of the serial bit-level representation on the basis of polynomial coefficient is needed. In this paper, we propose a new serial bit-level Mastrovito multiplier schemes. We are in terms of the complexities of the time, the proposed multiplier schemes available in the literature have shown to outperform existing serial bitlevel schemes. In addition, the proposed use of multiple schemes, we present a new hybrid-double multiplication architectures. Best of our knowledge, this represents the first time using a polynomial coefficient of such a hybrid structure is proposed. The serial bit-level patterns and schemes presented by the proposed hybrid-double multiplication architectures (10 schemes in total) are implemented over both $ GF (2^{163})$ and $GF(2^{233})$ , and experimental results are presented.