Design and Simulation of Low Power Cmos Ternary Full Adder

Abstract

Ternary system is defined as a number system with radix-3. With a lot of new ternary circuits being proposed as an alternative to the digital logic, we consider a step further that in this paper we proposed to design a Ternary coded Decimal (TCD) adder circuit based on CMOS technology. Unlike a Ternary adder, the TCD adder utilizes 3-bit Ternary coded Decimal (TCD) number as input and the resulting sum will also be in TCD form. The designing of TCD adder is depends on a new custom circuit for ternary adder which is modifying for less number of transistors. In the due course we will also highlight how non-conventional, custom designed circuits give area advantage compared to the Ternary k-map based methods.