Low-Power Programmable Prpg with Test Compression Capabilities

P. Snigdha Kamala, Sreenath Kashyap

Abstract


This paper depicts another programmable low power test compression strategy that allows shaping the test power envelope in a completely unsurprising, exact, and adaptable form by adapting the existing rationale BIST infrastructure. The proposed hybrid plan proficiently combines test compression with rationale BIST, where the two systems can work synergistically to convey great test. Exploratory outcomes obtained for industrial outlines show possibility of the proposed test conspire and are accounted for herein.


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