A Literature Survey on Ldpc Decoding of Nand Flash Memory by Using Array Dispersion

Abstract

The reliability of data stored in an high-density Flash memory devices tends to drop off rapidly because of the reduced cell size and multilevel cell technology. The Soft-decision error correction algorithms make use of multiple-precision sensing for reading memory which can solve this problem. They require a very complex hardware for high-throughput decoding method. In this method, we present a rate-0.97 (68254, 65536) summarized Euclidean geometry low-density parity-check code and its VLSI operation for increased throughput NAND Flash memory system. The aim employ the normalized a posterior probability (APP)-based algorithm, serial schedule, and unrestricted update, which will lead to simple functional unit, halve decoding iterations, and compact power consumption. The pipelined equivalent structural design is adopted for high-throughput decodes, and memory-reduction techniques are employed to minimize the total chip size. The proposed decoder method is implemented in 0.13-μm CMOS tools, and the chip size and power consumption of the decoder are compared with those that of a BCH (Bose–Chaudhuri–Hocquenghem) decoding circuit performance compared with the error-correcting presentation and throughput.