Design and implementation of the DFT using sleep approach and DTCMOS technique

Abstract

Design for testability (DFT) refers to hardware design styles or it is an added hardware  that reduces test generation complexity and test cost, also increases test quality. Sleep Convention  Logic (SCL) is an asynchronous logic style which is based on Null Convention Logic (NCL). In the  SCL the combinational blocks are made of threshold  gates. Now-a-days the power dissipation is a major problem in electronic devices. The importance for power management Integrated Circuit (PMIC) is emphasized as battery-powered portable electronics such as smart phone are commonly used. Due to this problem static power dissipation is highly increased. In this paper we propose the use of a new DTMOS scheme in DFT Design.