Design and Implementation of Hybrid Lut/Multiplexer Fpga Logic Architectures

Abstract

Hybrid configurable logic block architectures for field-programmable door clusters that contain a blend of query tables and solidified multiplexers are assessed toward the objective of higher logic thickness and zone decrease. Innovation mapping enhancements that objective the proposed architectures are additionally executed inside ABC. Both representing complex logic block and steering zone while keeping up mapping profundity. For fracturable architectures, the proposed design of this paper investigation the logic size, zone and power utilization utilizing Xilinx 14.2.