Graph Based Transistor Network Generation Method For Super Gate Design

Abstract

Transistor community optimization represents an effective way of enhancing VLSI circuits. This paper proposes a singular approach to routinely generate networks with minimum transistor rely, beginning from an irredundant sum-of-products expression as the input. The technique is able to supply each collection–parallel (SP) and non-SP transfer preparations, enhancing speed, strength dissipation, and place of CMOS gates. Experimental results display predicted profits in evaluation with associated processes.