A Novel Design of 16-Bit MAC Unit using Hybrid Variable Latency CSKA Structure for DSP Applications

Abstract

In this paper, we present an area efficient Multiply and Accumulator (MAC) structure using vedic multiplier and various carry skip adders. In this paper first we examine the area and delays of three types of carry skip adder designs. The first design is conventional CSKA using MUX. Second outline which utilizes applying link and incrementation plans to enhance the proficiency of the traditional CSKA (Conv-CSKA) structure. In addition, rather than using multiplexer logic, the CSKA makes utilization of AND-OR-Invert (AOI) as well as OR-AND-Invert (OAI) compound gates for the skip logic (CI-CSKA). The third CSKA design which implements variable stage size(VSS) CSKA and with the 8-bit parallel prefix adder (PPA) in order to reduce the delay. These CSKA adders are used in MAC implementations along with the 16x16 vedic multiplier and the results are studied. Verilog HDL is used for designing the circuits. The synthesis and simulation results are obtained using Xilinx ISE 14.7.