Implementation of High Speed Multiplier in DSP Applications Using Mesochronous Pipelining In FPGA

Swaroop Kumar Macherla


A novel mesochronous pipelining plan is depicted in this paper. In this plan, information and clock travel together. At any given time a pipeline stage could work on more than one information wave. The check time frame in the proposed pipeline plot is controlled by the pipeline arrange with biggest distinction between its base and most extreme deferrals. This is a huge execution pick up contrasted with customary pipeline plot where clock period is dictated by the phase with the biggest postponement. Additionally, the quantity of pipeline stages and pipeline registers is little. The clock circulation plot is basic in the mesochronous pipeline design. A 8-bit Wallace tree multiplier has been executed in mesochronous pipeline design utilizing unassuming TSMC 180-nm (drawn length 200 nm) CMOS innovation. The multiplier engineering and recreation comes about are portrayed in detail in this paper.


High performance, mesochronous pipeline, multiplier, pipelined system, register delays.

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