VLSI Design of a Novel LP-LFSR based programmable PRPG Architecture

Abstract

This paper describes a low-power (LP) programmable generator capable of  reducing pseudorandom take a look at patterns with desired toggling levels and increased fault coverage gradient compared with the best-to-date intrinsically self-test (BIST)- primarily based pseudorandom take a look at pattern generators. it's comprised of a linear finite state machine (a linear feedback register or a hoop generator) driving associate degree applicable section shifter, and it comes with variety of options permitting this device to supply binary sequences with preselected toggling (PRESTO) activity. We tend to introduce a technique to mechanically choose many controls of the generator providing straightforward and precise calibration. Identical technique is afterwards used to deterministically guide the generator toward take a look at sequences with improved fault-coverage-to pattern-count ratios. Moreover, this paper proposes associate degree disc take a look at compression technique that permits shaping the take a look at power envelope during a absolutely certain, accurate, and versatile fashion by adapting the PRESTO-based logic BIST (LBIST) infrastructure. The projected hybrid theme expeditiously combines take a look at compression with LBIST, wherever each techniques will work synergistically to deliver top quality tests. Experimental results obtained for industrial styles illustrate the practicableness of the projected take a look at schemes and are rumored herein.