Design and Implementation of Area-Efficient Dual-Mode Double Precision Floating Point Division

Abstract

Floating point division is a center number-crunching broadly utilized as a part of logical and building applications. This paper proposed engineering for twofold precision floating point division. This engineering is intended for double mode usefulness, which can either register on a couple of twofold precision operands or on two sets of single precision operands in parallel. The engineering depends on the arrangement development multiplicative approach of mantissa calculation. For this, a novel dual mode Radix-4 Modified Booth multiplier is planned, which is utilized iteratively in the design of double mode mantissa calculation. Other key parts of floating point division stream, (for example, driving one-identification, left/right unique shifters, adjusting, and so on.) are additionally re-intended for the double mode operation. The proposed double mode engineering is orchestrated utilizing UMC 90nm innovation ASIC execution. Two forms of proposed design are exhibited, one with single stage multiplier and another with two phase multiplier. Contrasted with an independent twofold precision division design, the proposed double mode engineering requires 17% to 19% additional equipment assets, with 3% to 5% period overhead. In contrast with earlier craftsmanship on this, the proposed design out-performs them regarding required area, era and throughput.