High Performance of CMOS 1-Bit Full adder cell Based on Novel Techniques

Abstract

In this paper we presented low spillage 10T one-piece full adders cells are proposed for versatile applications. The investigation has been performed on different process also, circuits strategies, the examination with spillage control. We presented another transistor resizing approach for 1bit full viper cells to decide the ideal rest transistor estimate which diminish the spillage power and region to limit spillage current. We have performed recreations utilizing Cadence Virtuoso 45nm standard CMOS innovation at room temperature with supply voltage of 0.71V. Recreations have been moreover analyzed for different VDD. Subsequently configuration rules have been inferred to choose the most reasonable topology for the plan highlights required. This paper moreover proposes a novel figure of legitimacy to practically think about 1-bit adders executed as a chain of one bit full adders. The CMOS spillage current at the process level can be diminished by some execute on profound sub micron technique. The circuit level strategy is lessened power utilization at abnormal state. In this paper we reproduce the 10T Adder utilizing numerous systems both circuit level, process level.