Designing Tunable Subthreshold Logic Circuits Using Adaptive Feedback Equalization

Abstract

In embedded applications, ultralow-power sub-threshold logic circuits have extensive use with limited energy budgets. By operating in the sub-threshold regime, we can achieve minimum energy utilization of digital logic circuits. However, in this regime process variations can result in up to an order of magnitude variation in ION/IOFF ratios. It leads to timing errors and have a harmful effect on the working of the sub-threshold circuits. These timing errors become often in scaled technology nodes and hence process variations are highly common. Therefore, mechanisms to check these timing errors while minimizing the energy consumption are necessary. In this paper, we propose a tunable adaptive feedback equalizer circuit which is  used with a sequential digital logic to check the process variation effects and reduce the dominant leakage energy component in the sub-threshold digital logic circuits. We also present detailed energy-performance models of the adaptive feedback equalizer circuit.