A Novel High Performance Sense Amplifier based Low Power SRAM Memory cell

Vishani P Sheth, Towheed Sultana


Reduced energy potency has invariably been the foremost aim of the custom and automatic digital circuit techniques. Though increasing nano-devices area unit expected to exchange the prevailing MOSFET devices, aloof from being as mature as semiconductor devices and their full potential and promise are a few years faraway from being sensible. The analysis represented during this exposition consists of 4 main components. it's a replacement circuit design of a difference limen logic flip- flop known as n-NOR. The NNOR gate may be an edge-triggered multi-input serial cell whose next state perform is a function of its inputs. a replacement approach, known as hybridisation, that replaces flip flops and components of their logic comes with n-NOR cells is represented. The ensuing hybrid circuit, that consists of standard logic cells and n-NORs, is shown to own considerably less power consumption, smaller space, less standby power and fewer power variation.It is a replacement design of a field programmable array, known as field programmable threshold logic array (FPTLA), during which the quality operation table (LUT) is replaced by a NNOR is represented. The FPTLA is shown to own the maximum amount as eightieth lower energy delay product compared to traditional FPGA exploitation well- better-known FPGA modeling tool known as VPR. it's a unique clock skewing technique that creates use of the completion detection feature of the differential mode flip- flops is represented. This clock skewing methodology improves the world and power of the ASIC circuits by increasing slack on temporal order ways.

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