Low Power Test Pattern Generator using LFSR for Speed up the ATP Process

Abstract

A new test generation methodology is proposed that takes advantage of shared memory multi-core systems. Appropriate parallelization of the main steps of ATPG allocates resources in order to minimize workload duplication and multithreading race contention, often encountered in parallel implementations. The proposed approach ensures that the obtained acceleration grows linearly with the number of processing cores and, at the same time, keeps the test set size close to that obtained by serial ATPG. The experimental results demonstrate that the proposed methodology achieves higher degree of speed-up than comparable state-of-the-art multi-core based tools, while maintains similar test set sizes.