CMOS Based Full Adder and its Scaling for Speed and Power Consumption

Abstract

A fast and energy-efficient Full Adder plays important role in electronics industry especially digital signal processing (DSP), image processing and performing arithmetic operations in microprocessors. Full Adder is such an important element which contributes substantially to the total power consumption of the system. In this paper, proposed 2-bit Full Adder has been taken which is then analyzed and a comparative study of the silicon area and the power consumption has been done in the circuit using different channel lengths such as 90nm, 70nm and 50nm. The designed circuit has shown a remarkable reduction in the consumed power of 94.5% and a reduction of 75.03% in consumed area in 50nm foundry as compared to 90nm COMS technologies. The designed Full adder are compared in terms of power consumption and surface area product using DSCH and MICROWIND tools.