Design and Implementation of Multiplier Design Using Fixed-Width Replica Redundancy Block for Low Power Applications

Abstract

In this we are  proposing a reliable low-power multiplier design by adopting algorithmic noise tolerant (ANT) architecture with the fixed-width multiplier to build the reduced precision replica redundancy block (RPR). The proposed ANT architecture can meet the demands of effective utilization of area, reduced power consumption with  high precision values. We design the fixed-width RPR with error compensation circuit via analyzing of probability and statistics. Here we are using the input correction vector(ICV) and minor input correction vector(MICV) of partial products terms to lower the truncation errors, so that the complexity in error compensation circuit hardware can be simplified. In a 12 × 12 bit ANT multiplier, we are using DADDA multiplier for the multiplication in the Main DSP.