Area Reduction Exclusive OR/NOR Design Using SCDM

Abstract

The XOR/XNOR logic gates plays a crucial job in digital circuits which are full adders, compressors, parity generators and comparators. These logic gates are taken in critical path of these systems, which considerably influenced the system characteristics. An optimized layout is desired to neglect any degradation at the output voltage, devour much less power, and feature a less wide variety of transistors to implement the circuit.  Two distinct approaches of three-input exclusive-OR (XOR) feature at transistor stage with a systematic cell design methodology (SCDM) are proposed in this paper. For low power and high speed (LPHS) applications, these approaches are well desirable. The proposed designs comprises low dynamic and short-circuit power consumption and their internal nodes scatter negligible leakage power, which ends up in low average power consumption. Those designs are used to improve the overall performance, voltage ranges, and the driving functionality and decreasing the quantity of transistors in the primary structure of the designs. By using MICROWIND/DSCH 180 nm technology two different approaches of 3-input XOR/XNOR circuits are designed and simulation results are generated by the usage of HSPICE 180 nm technology. In terms of speed, power consumption and transistor count the performance of proposed circuits are better than existing circuits.