VLSI Design of a Novel Wallace Tree Multiplier for an FIR Filter

Abstract

The Wallace tree multiplier is considered as faster, than a simple array multiplier and is an effective application of a digital circuit which multiplies two integers. A Wallace tree multiplier is a parallel multiplier that uses the carry save addition algorithm to reduce the quiescene. There are numerous researchers dealt on the design of progressively more efficient multipliers. The main purpose is to accomplish higher speed and lower power consumption even while occupying condensed silicon region. Wallace tree multiplier are rapid multipliers, uses full and half adder .As far as range and power the execution of XOR-XNOR gates and MUX effective. The proposed Wallace tree multiplier technique is far superior compared to traditional method. In this paper we present FIR filter implementation of Wallace multiplier, as the Extension.