Design of Low Speed High Power Digital Filter in Communication Systems

K. Rajendra Prasad, Yashpal Singh


In  this  paper,  a  design  methodology  to  implement  low-power   and   high-speed   2nd   order   recursive   digital   Infinite    Impulse  Response  (IIR)  filter  has  been  proposed.  Since  IIR  filters  suffer  from  a  large  number  of  constant  multiplications,  the  proposed  method     replaces     the     constant     multiplications     by     using     addition/subtraction and shift operations. The proposed new 6T adder cell   is   used   as   the   Carry-Save   Adder   (CSA)   to   implement   addition/subtraction operations in the design of recursive section IIR filter   to   reduce   the   propagation   delay.   Furthermore,   high-level   algorithms  designed  for  the  optimization  of  the  number  of  CSA  blocks  are  used  to  reduce  the  complexity  of  the  IIR  filter.  The  DSCH3  tool  is  used  to  generate  the  schematic  of  the  proposed  6T  CSA based shift-adds architecture design and it is analyzed by using Microwind  CAD  tool  to  synthesize  low-complexity  and  high-speed  IIR  filters.  The  proposed  design  outperforms  in  terms  of  power,  propagation  delay,  area  and  throughput  when  compared  with  MUX-12T, MCIT-7T based CSA adder filter design. It is observed from the experimental  results  that  the  proposed  6T  based  design  method  can  find  better  IIR  filter  designs  in  terms  of  power  and  delay  than  those  obtained by using efficient general multipliers. 


CSA Full Adder, Delay unit, IIR filter, Low-Power, PDP, Parametric Analysis, Propagation Delay, Throughput, VLSI.Vlsi Design High Speed Low Power Digital Filter In

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