VLSI Design of a Novel Pre Encoding Multiplier Using DADDA Multiplier

Abstract

The most effective way to increase the speed of a multiplier is to reduce the number of the partial products because multiplication precedes a series of additions for the partial products. To reduce the number of calculation steps for the partial products NR4SD encoding is used  mostly where CSA has taken the role of increasing the speed to add the partial products. In this NR4SDˉ and NR4SD⁺ are used to reduce no of partial products. To further implement the 

Performance of the multiplier we are using the DADDA multiplier. The experimental results have shown that the proposed multiplier outperforms the conventional multiplier in terms of power and speed of operation. In this  paper we used  Xilinx-ISE  tool  for  logical  verification,  and Simulation.