High-Throughput Turbo Decoder with Parallel Architecture for Lte-Wireless Communication Standards

Abstract

This work focuses on the VLSI design aspect of high speed maximum a posteriori (MAP) probability decoders which are intrinsic building-blocks of parallel turbo decoders. For the logarithmic-Bahl–Cocke–Jelinek–Raviv (LBCJR) algorithm used in MAP decoders, we have presented an ungrouped backward recursion technique for the computation of backward state metrics. Unlike the conventional decoder architectures, MAP decoder based on this technique can be extensively pipelined and retimed to achieve higher clock frequency. Additionally, the state metric normalization technique employed in the design of an add-compare-select-unit (ACSU) has reduced critical path delay of our decoder architecture. We have designed and implemented turbo decoders with 8 and 32 parallel MAP decoders in 90nmCMOStechnology. VLSI implementation of an 8 parallel turbo-decoder has achieved a maximum throughput of 439 Mbps with 0.11 n J/bit/iteration energy-efficiency. Similarly, 32parallel turbo-decoder has achieved a maximum throughput of 1.138 Gbps with an energy-efficiency of 0.079 n J/bit/iteration. These high-throughput decoders meet peak data-rates of 3GPP-LTEandLTE-Advanced standards.