VLSI Implementation of AES Algorithm using Rijndael algorithm

Abstract

In this paper we present a high-performance, high throughput, and area efficient architecture for the VLSI imple- mentation of the AES algorithm. The subkeys, required for each round of the Rijndael algorithm, are generated in real-time by the key-scheduler module by expanding the initial secret key, thus reducing the amount of storage for buffering. Moreover, pipelining is used after each standard round to enhance the throughput. A prototype chip implemented using 0.35µ CMOS technology resulted in a throughput of 232M bps for iterative architecture and 1.83ttbps for pipelining architecture.