Design a high speed fft using carry skip adder for communication

Abstract

A carry skip adder (CSKA) structure is presented which has lower power consumption with a higher speed. The performance of the conventional CSKA is improved by achieving the speed enhancement by applying concatenation and incrementation schemes. The existed structure utilizes AND-OR-INVERT (AOI) and OR-AND-INVERT (OAI) compound gates for the skip logic. The existed system is complex in area. The Fast Fourier Transform (FFT) is an efficient algorithm to compute the DFT and its inverse.  The FFT plays a key role in the field of communication systems like Digital Video or Audio Broadcasting, Wireless LAN with Standards of IEEE 802.11, High Speed Digital Subscriber Lines. This paper utilizes the implementation of folding technique using radix-2 DIT FFT algorithm. The proposed algorithms are used in radix-2 butterfly in all stage. The proposed algorithm is area efficient and consumed delay in previous algorithm. The all design are implementation vertex-6 device family Xilinx software.