Available online: https://edupediapublications.org/journals/index.php/IJR/ P a g e | 5674 Design of Aging-Aware Reliable Multiplier with Adaptive Hold Logic Using Variable Latency Techniqu
Abstract
Digital multipliers are among the most critical arithmetic functional units. . Therefore, it is important to design reliable high-performance multipliers. In this paper, we propose an agingaware multiplier design with a novel adaptive hold logic (AHL) circuit. The multiplier is able to provide higher throughput through the variable latency and can adjust the AHL circuit to mitigate performance degradation that is due to the aging effect. Moreover, the proposed architecture can be applied to a column- or row-bypassing multiplier.
Full Text:
PDFCopyright (c) 2018 Edupedia Publications Pvt Ltd
![Creative Commons License](http://licensebuttons.net/l/by-nc-sa/4.0/88x31.png)
This work is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International License.
All published Articles are Open Access at https://journals.pen2print.org/index.php/ijr/
Paper submission: ijr@pen2print.org