Input Based Dynamic Reconfigurable Approximation Architecture for MPEG Encoders

Nagam Lavanya sree, N. Anil


The field of approximate computing has received significant attention from the research community in the past few years, especially in the context of various signal processing applications. Image and video compression algorithms, such as JPEG, MPEG, and so on, are particularly attractive candidates for approximate computing, since they are tolerant of computing imprecision due to human imperceptibility, which can be exploited to realize highly power-efficient implementations of these algorithms. However, existing approximate architectures typically fix the level of hardware approximation statically and are not adaptive to input data. This paper addresses this issue by proposing a reconfigurable approximate architecture for MPEG encoders that optimizes delay by proposing 64 bit reconfigurable CLA. Toward this end, we design 64 bit reconfigurable adder/subtractor blocks (RABs), which have the ability to modulate their degree of approximation, and subsequently integrate these blocks in the motion estimation and discrete cosine transform modules of the MPEG encoder. Experimental results show that our approach will occupy only 506 LUTs of SPARTAN 3E FPGA over total 9312 LUTs with a delay of 24.047ns.

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