Design an Efficient Architecture of Fft-Based On Cska

Sandireddy Rama Tireesha, M. Naga Swapna


In this we are going to discuss about the structure of carry skip adder (CSKA) which performs the operation with high speed and low energy consumption. By using the both concatenation and increment techniques we can increase the efficiency of carry skip adder. For the purpose of skip logic we use the AND-OR and OR-AND inverter gates.The realization of carry skip adder circuit is done by using two styles, one is fixed stage size style and another is variable stage size style. By adding a hybrid variable latency extension to the proposed structure we can reduce the power consumption and as well as speed also increases. In the same way to increase the slack time we usea modified parallel structure. Now to detect and correct the errors we use the fault tolerant method. One of the main examples of this fault tolerant method is fast Fourier transform (FFT). At last   fault tolerant parallel FFT efficiency is increased by protecting the FFTS (.i.e) FFT using CSKA.

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