Design A Fault Tolerant Fft’s Using Ahl Logic And Razor Flipflop

Sudanagunta Kiran, N. Prakash Babu


The complexity of communications and signal processing circuits increases every year. This is made possible by the CMOS technology scaling that enables the integration of more and more transistors on a single device. This increased complexity makes the circuits more vulnerable to errors. At the same time, scaling means that transistors operate with lower voltages and are more susceptible to errors which are caused by noise and manufacturing variations. Soft errors cause a reliability threat to modern electronic circuits. This makes protection against soft errors which is a requirement for many applications. Communications and signal processing systems do not have any exceptions to this trend. An interesting option is to utilize algorithmic-based fault tolerance (ABFT) techniques which is try to exploit the algorithmic properties to detect and correct errors. Signal processing and communication applications are well suited for ABFT technique. Several protection schemes have been proposed to detect and correct errors in FFTs. Among those, the Perseval or sum of squares check is the most widely known protection scheme. In proposed system, two improved protection schemes that combine the use of error correction codes and Perceval checks are proposed and evaluated.

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