High Speed Implementation of Novel Adder Based On Parallel Prefix Technique

Abstract

Fast Fourier transform (FFT) coprocessor, having a significant impact on the performance of communication systems, has been a hot topic of research for many years, since many signal processing applications need high throughput more than low latency. The FFT function consists of consecutive multiply add operations over complex numbers, dubbed as butterfly units. Recently, floating-point (FP) arithmetic is applied to FFT architectures, specifically butterfly units has become more popular. It offloads compute-intensive tasks from general-purpose processors by dismissing FP concerns for example scaling and overflow/underflow. However, the major downside of FP butterfly is its slowness in comparison with its fixed-point counterpart. So, parallel prefix (PP) multiplier is proposed which is high speed. The Parallel prefix multiplier provides fast of operation when compared with the FP multiplier. It gives better performance than the existed system.