Fault detection of NOC Routers in FIFO memory

Ch. Kalpana, M.S. Shyam


We have proposed an online transparent test technique for first-input first-output (FIFO) buffers and routing logic present within the routers of the NoC infrastructure. Our contributions are as follows. A transparent SOA-MATS++ test generation algorithm has proposed targeting in-field permanent faults developed in SRAM based FIFO memories and it has been utilized to perform online and periodic test of FIFO memory present within the routers of the NoC. In addition, we have also proposed an online test technique for the routing logic that is performed simultaneously with the test of buffers. The proposal involves two ways of utilizing the unused portion of the header flits of the incoming data packets in transporting the test patterns. First, deterministic test patterns for the routing logic generated by Tetramax are placed in the unused fields of the header flit and are transported during the normal cycle. Second, the pseudorandom patterns in the synthetic data traffic used during normal operation and arriving at the routing logic are considered as test patterns. Fault coverage is estimated for either of the two proposals.

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