Multilevel Inverter Topology with Reduced Switch Count

G. Ramya, M. Vaidehi


Multilevel Inverters have created a new wave of interest in industries and research. While the classical topologies proved to be a viable alternate in wide range of high power medium-voltage applications, there has been an active interest in the evolution of newer topologies. Reduction in overall switch count as compared to the classical topologies has been an important objective in the recently introduced topics. In this paper a new topology for Multilevel inverters is proposed, which reduces the number of switches when compared to previous topologies. In this proposed topology we could able to get seven levels with eight switches, one input source and three input capacitors. We can also enhance the levels to nine level with one more switch adding to the proposed topology and with proper switching sequence. The total circuit configuration is developed in Matlab/simulink software. 

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