Design a Novel Approach to Verification the Faults in Circuit

Abstract

A Globally Asynchronous Locally Synchronous (GALS) modeling tool is introduced for circuit verification. In particular, this approach enables the visualization of point-to-point causality of problems occurring among various parts of the system which are more difficult for analyzing. The reliability and quality improvements are essential for digital circuits as their complexity and density increases. Validation of VLSI circuits becomes more difficult with higher test cost. In Circuit Under Test (CUT) architectures, the Test Pattern Generator (TPG) utilizes Linear Feedback Shift Register (LFSR) generates pseudo random patterns that increases the switching activity of test patterns. The test pattern generator generates a multiple single input change vector which increases the accuracy of test response. The TPG is used in test-per-scan scheme. A combinational circuit is used as the circuit under test, and the output response of CUT is stored in Look Up Table (LUT) for error comparison in LUT method of verification. Reversible technique is also used for the testing the circuit under test.