Design of A Reversible Fault Tolerant Fft Using Reversible Gates

Abstract

In this paper we are going to see the design of reversible fault tolerant architecture of FFT. This logic elements are taken from look up tables depends upon the field programmable gate array (.i.e.) FPGA. Here we are using proposed logic elements like master slave flip flop, D-Latch and multiplexer. To design the reversible fault tolerant architecture, D-Latch, master slave flip flop(MSFF) and multiplexers we propose a new fault tolerant reversible gates with FFT. Compared to the existed system this proposed system is much better and it gives better results like in terms of gates there is an increment of maximum value. There is not only increment in gates but also there is an incrementing terms of quantum cost and decrease unit delay.