Design of High Performance Scan Register Insertion on Integer Arithmetic Cores

Abstract

Insertion of Scan flip–flop for testability invites in aiding design for overhead additional hardware thereby performing the deteriorating of the circuit. In this paper, we shall demonstrate a FPGA based implementation for Finite State Machines in the  insertion of  scan registers and data path pipelined circuits with no overhead or compromise in performance of the hardware. All our designs which as been proposed have been realized using a low–level design methodology relatively involving target FPGA family based instantiation primitive, coupled with their constrained placement on the fabric Xilinx FPGA. Implementation results clearly reveal the our proposed architectures in  superiority comparison to equivalent circuits derived through modelling  behavioural with respect to speed  and area. Additionally, our proposed scan register rcircuit inserted  with circuits designed without compare favourably for scan flip–flops. Coupled with this, lies the ease of an of the corresponding Hardware Description Language (HDL) automated generation  and placement constraints and their portability among other FPGA families from advanced  Xilinx