Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications

Abstract

The (DSRC)  dedicated short-range communication is an intelligent transportation system to push  an emerging technique in our daily life.  DSRC standards generally adopt FM0 and enhancing the signal reliability, Manchester codes to reach dc-balance. Nevertheless, the VLSI architecture for both coding-diversity between the Manchester codes limits the potential to design a fully reused. in this paper the FM0, to overcome this limitation (SOLS) similarity-oriented logic simplification technique is proposed. SOLS technique increases the hardware utilization rate from 57.14% to 100% for both  FM0 and  Manchester encodings.  this paper evaluated the performance of post layout simulation in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18-µm 1P6M CMOS technology . The maximum operation frequency is 2 GHz and 900 MHz for Manchester and FM0 encodings, respectively. The power consumption is 1.58 mW at 2 GHz for Manchester encoding and 1.14 mW at 900 MHz for FM0 encoding. The core circuit area is 65.98 × 30.43 µm2. The encoding capability of this paper can fully support the DSRC standards of America, Europe, and Japan. This paper not only develops a fully reused VLSI architecture, but also exhibits an efficient performance compared with the existing works. Index Terms—Dedicated short-range communication (DSRC), FM0, Manchester, VLSI.