Implementation of High Performance FIR Filter Using Low Power Multiplier and Adder

Abstract

The ever increasing growth in laptop and portable systems in cellular networks has intensified the research efforts in low power microelectronics. Now a day, there are many portable applications requiring low power and high throughput than ever before. Thus, low power system design has become a significant performance goal. So this paper is face with more constraints: high speed, high throughput, and at the same time, consumes as minimal power as possible. The Finite Impulse Response (FIR) Filter is the important component for designing an efficient digital signal processing system. So, in this paper author trying, a FIR filter is constructing, which is efficient not only in terms of power and speed but also in terms of delay. When consider the elementary structure of an FIR filter, it is found that it is a combination of multipliers and delays, which in turn are the combination of adders. . This paper presents an efficient implementation and analysis for performance evaluation of multiplier and adder to minimize the consumption of energy during multiplication and addition methodology to improve the performance by compares different type of Multipliers and adder, respectively. By using, power comparison result of adders and multiplier, choice low power adder and multiplier to implementation of high performance FIR filter.