Design A Multiplier Using Reversible Gates Shift Register

Abstract

This paper proposes a low-power and area-efficient shifter design using reversible logical gates. The area and power consumption are reduced by replacing flip-flops with pulsed latches. This method solves the timing problem between pulsed latches through the use of multiple non-overlap delayed pulsed clock signals instead of the conventional single pulsed clock signal. The shift register uses a small number of the pulsed clock signals by grouping the latches to several sub shifter registers and using additional temporary storage latches. Here the reversible gate designs called NSG. The purpose of NSG is to implement in all logical Boolean operations. The reversible gates that perform reversible logic synthesis are Feynman gate, toffoli gate, fredkin gate, peres gate etc., and some of other reversible gates. By using these reversible N.S gate we make a multiplier that gives very efficient output.