Realization of Building Blocks of Floating Point Butterfly Architecture

Abstract

Fast Fourier transform (FFT) coprocessor, having a noteworthy crash on the performance of communication systems. The FFT function consists of uninterrupted multiply add operations over complex statistics, dubbed as butterfly units. By applying floating-point (FP) arithmetic to FFT architectures, expressly butterfly units, has become more popular recently. It off-load compute-intensive errands from general-purpose processors by dismissing FP (e.g., scaling and overflow, underflow etc). However, the key downside of FP butterfly is its slowness in contrast with its fixed-point equal. This reveals the spur to develop a high-speed FP butterfly architecture to moderate FP slowness. This brief presents fast FP butterfly unit using a devised FP fused-dot-product-add (FDPA) unit, based on carry select adder (CSA) in existing. This brief proposes a fused floating-point operations and applies them to the implementation of fast Fourier transform (FFT) processors. The fused operations are a two-term dot product and an add-subtract unit, FP fused-dot product-add (FDPA) unit, based on binary signed-digit (BSD) representation and compared with CSA representation. In this brief different blocks used in floating point Butterfly Architecture are designed. Simulation results are observed using Cadence tool.