Execution of Low Power Optimizing Chien Search Usage in the BCH Decoder

Abstract

Designing multipliers that are high speed, low power, and regular design are of great interest to research. The multiplier speed can be increased by reducing the generated partial products. Many attempts have been made to reduce the number of partial products generated in the multiplication process, one of which is the multiplier of the matrix. The average sum of the matrix multiplier was used to summarize the transport products in a short time. The attainment of high-speed integrated circuits with low power consumption is a major concern for VLSI circuit designers. Most arithmetic operations are performed with a multiplier, which is the main element that consumes energy in digital circuits. In essence, the multiplication process is performed on hardware in terms of editing and adding. The adder optimization has led to improved multiplier performance. This project proposes a complete modified adder that uses a multiplexer to achieve a low power consumption of the multiplier. In order to analyze the efficiency of the proposed project, the conventional structure of the multiplier matrix is used. The designs are developed with Verilog HDL and the features are verified by simulation with Xilinx. In this project, the modified full adder that uses the multiplexer is compared to the traditional full hardware and speed adder.