High-efficient approximate multiplier designed using modified 4-2 compressor

Abstract

In this modern era, many of the digital systems are error resilient which allows us to take the advantage of approximate computations. This makes the use of replacement of exact computing units by their counterparts. Approximate computing can also decrease the complexity at the designing levels with an increase in performance and power efficiency. Adders and multipliers are the basic buildings blocks of many digital applications. These blocks can be approximated in several ways. Research works are on the rise at many levels on approximate computing. Approximation at designing level is more advantageous as the modifications at this level much easier than the preceding levels.This paper presents a method of designing an approximate multiplier with a modified structure of 4-2 compressor.4-2 compressor is designed with two full adders in general. In this paper these full adders are designed in two methods, i.e., one is by using AVLG(adaptive voltage level at ground) technique with 10transistors, and the second method uses 8 transistors.Outputs from these adders are again fed to a half adder with an x-or gate at its output. This improves the accuracy of compressor. The multiplier is designed using Xilinx in the frontend. And the 4-2 compressor module is also designed in Xilinx on front-end and in backend by using micro wind 3tools.