A Fast Method for Error Correction Codes of Single Bit with Rapid Decoding For A Subset Of Critical Bits.

Abstract

Single error correction (SEC) codes are widely usedto protect data stored in memories and registers. In some applications, such as networking, a few control bits are added tothe data to facilitate their processing. For example, flags to mark the start or the end of a packet are widely used. Therefore, it isimportant to have SEC codes that protect both the data and the associated control bits. It is attractive for these codes to provide fast decoding of the control bits, as these are used to determine the processing of the data and are commonly on the critical timing
path. In this brief, a method to extend SEC codes to support a fewadditional control bits is presented. The derived codes support fastdecoding of the additional control bits and are therefore suitablefor networking applications