Design and Analysis of Kogge-Stone and Han-Carlson Adders in 130nm CMOS Technology

Abstract

Adders find applications in Arithmetic and Logic Units (ALUs), microprocessors, DSP systems and ASIC systems. An efficient adder can be of greater assistance in designing of any arithmetic circuits. The various types of adder design are available each with their own advantages and disadvantages. In this paper, we proposed the comparative analysis between the 8-bit Kogge-Stone and Han-Carlson parallel prefix adders. Parallel prefix computation algorithm is employed to improve the speed of the addition. Parallel Prefix Adders (PPA) are extensively used to make a wide range of design tradeoffs in terms of area, delay and power. In this paper, adders are designed and simulated in 130 nm technology using Tanner EDA tool.