Degin of PPA-B.K Adder For Fast Computing

Abstract

In this paper, the design an  residue number system reverse converters based on Brent Kung  adders is analyzed. The parallel prefix adder provides high speed and reduced delay arithmetic operations such as addition multiplication but it is not widely used since it suffers from high power consumption and high area on chip. Hence, a Brent Kung adder component is presented to perform fast modulo addition in Residue Number System reverse conversion. The proposed components are not only results in fast arithmetic operation and it also highly reduced the hardware density since it requires fewer amount of logic gates. In this work, the proposed components are implemented in different moduli sets reverse converter designs and the performances are compared for different values of n.