Analysis of High Efficiency Low Density Parity-Check Code Encryption

Sk. Reshma, Sk. Sajida, Sk. Reshma, Sk. Affroz Banu, D. Pratap Kumar


In this study, we propose a low power, high efficient Low Density Parity-Check Code (LDPC) Decoder Architecture for error detection and correction applications. LDPC codes have been adopted in latest wireless standards such as satellite and mobile communications since they possess superior error detecting and correcting capabilities. As technology scales, memory devices become larger and more powerful and low power consumption based error correcting codes are needed. This study discusses the design and analysis of check node unit and variable node unit in LDPC decoder. The architecture is synthesized and Xilinx and simulated using modelsim which is targeted 90nm device. Synthesis report shows that the proposed architecture reduces the hardware utilization and power consumption when compared to the conventional architecture design.

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