Low Power BIST based Multiplier Design and Simulation using FPGA

MR. D. SRIDHAR, G. Kalyani, B. Veerane, Ch.L. Pavan Kumar Gupta, E. Phani Pavan Prakash, CH. Akhil Babu


The ever increasing applications of integrated circuits in the day-to-day useful electronic gadgets is the driving force for the development of low power designs of configurable hardware designs. High speed and low power are the main parameters that are targeted by modern circuit designers. Among the fastest increasing applications the audio and video signal processing applications are growing at a very high rate. Mobile applications have increased the technological improvements for digital signal processing applications. Multipliers are the very important logic operational unit of any processing unit in digital signal processing applications. The speed and performance of multiplier is among the efficiency improvement parameters of any digital hardware design. Another important feature of hardware designs is self -testing ability. This feature provides reliability to the hardware mainly in case of configurable hardware applications. The built-in-self-test (BIST) feature helps in quick diagnosis of the hardware functional authenticity. This paper presents a BIST based implementation of a multiplier. The proposed design is realized using Xilinx Tool using VHDL. A low power Test Pattern Generator (TPG) is involved in the design for self-test design realization.



Built-In-Self-Test, Test Pattern Generator, Linear Feedback Shift Register, Xilinx, VHDL.

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