A Modified SRAM Based Low Power Memory Design

Abstract

The present world aims in designing low power devices due to the rampant usage of portable battery powered gadgets. The proposed static random access memory (SRAM) design furnishes an approach towards curtailing the hold power dissipation. The design uses a tail transistor which aids in limiting the short circuit power dissipation by disrupting the direct connection between supply voltage and ground. This tail transistor also brings down the subthreshold current by providing stacking effect, which subsequently reduces hold power dissipation. A supply voltage of 0.8V is used which makes it eligible for low power applications. The designed SRAM cell has single ended write and read operations and is simulated using Cadence 45nm CMOS technology. Statistical and corner analysis is also performed for the proposed design for its robustness. The proposed SRAM cell has a hold power dissipation of 4.74154pW which is much less as compared to the standard 6T SRAM cell.