Design of 3t Gain Cell for Ultra Low Power Applications

Abstract

Design of a power efficient SRAM cell is one of the most important factor in order to achieve better chip performance. This paper presents a stable SRAM Gain Cell for low power applications. The 6T SRAM has been the traditional choice for the implementation of embedded memories due to its high-access speed and refresh-free static data retention.However, the 6T bit cell has several drawbacks in modern systems, which includes its large transistor count. In order to provide full CMOS logic compatibility a gain-cell (GC)-embedded DRAM (eDRAM) consisting of 3-transistor (3T), GC-eDRAMs which provides a reduced silicon footprint, along with inherent two-port functionality, nonratioedcircuit operation, and very low static leakage currents from VDD to GND. With the benefit of read and write access,we modify the 8-TSRAM cell as 3-T SRAM cell with transmission gate that reduces the read and write time access with comparatively low power and eliminating the usage of signal booster. In this paper we designed the 3T GC cell by using MICROWIND/DSCH 180 nm technology and simulation results obtained by using HSPICE 180 nm technology.