Reliable Low Power Multiplier Design Using Reduced Precision Redundancy by Wallace Architecture

P.Lakshmi Neeraja, Ch.Rajesh Babu


In this paper, we have a tendency to propose a reliable low-power multiplier design by adopting Wallace multiplier design to make the reduced precision replica redundancy block (RPR). The projected Wallace multiplier factor design will meet the demand of high precision, low power consumption, and space efficiency. The partial product terms of input correction vector and minor input correction vector to lower the truncation errors, the hardware complexness of error compensation circuit may be simplified. In a very 12 ×12 bit Wallace multiplier factor, total real time delay and power consumption in our Wallace style may be saved by 22% as compared with the state-of-art ANT Design.

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