Design and Implementation of Novel Area Efficient Scan Based Lbist Using Lp Lfsr

Abstract

Testing is a fundamental step in Very-Large-Scale Integration (VLSI) design. There are two major steps in VLSI testing. They are Test Generation (TG) and Test Application (TA) . The objective of TG is to produce test patterns for adequate testing and TA is the process of applying those test patterns to the CUT and analyzing the output response. The whole process is performed by LBIST. To handle the increasing complexity of testing VLSI circuits is to incorporate Logic Built-In Self Test (LBIST) structures. However, LBIST architecture calls for increased area overhead. It is very important to keep this area overhead to a minimum. And by applying test vectors Power Droop (PD) may appear in LBIST which will generate a delay affect on the circuit under test (CUT) and it is recognized as a fault. So In this paper, we designed a novel area efficient scan-based LBIST, and it is achieved by using the LP-LFSR and also by proper modification of test vectors. As a result, 72.5% of area and power droop (pd) of proposed system is diminished than the existing method and by SA high fault coverage is also achieved. The proposed design architecture has been coded in VERILOG HDL and the software used is Xilinx